System Integration Unit (SIU)
MPC5644A Microcontroller Reference Manual, Rev. 6
392
Freescale Semiconductor
16.6.5
System Reset Control Register (SIU_SRCR)
The System Reset Control Register (SIU_SRCR) allows software to generate either a Software System
Reset or Software External Reset. The Software System Reset causes an internal reset sequence, while the
Software External Reset only causes the external RSTOUT pin to be asserted for the predetermined
number of clock cycles (refer to
). When written to one, the SER bit automatically
clears after the clock count expires. If the value of the SER bit is one and a zero is written to the bit, the
bit is cleared and the RSTOUT pin is negated regardless if the clock count has expired.
Figure 16-5. System Reset Control Register (SIU_SRCR)
29–3
0
BOOTCFG[0:1
]
Reset Configuration Pin Status
The BOOTCFG field holds the value of the BOOTCFG[1] pin that was latched on the last
negation of the RSTOUT pin. The BOOTCFG field is used by the BAM program to
determine the location of the Reset Configuration Word. See
for a translation of the Reset Configuration Half Word location from the
BOOTCFG field value.
0b00: Boot from internal flash memory (default)
0b01: FlexCAN / eSCI boot
0b10: Boot from external memory (no arbitration)
0b11: Reserved
31
RGF
RESET Glitch Flag
This bit is set by the MCU when the RESET pin is asserted for more than 2 clock cycles,
but less than the minimum RESET assertion time of 10 consecutive clock cycles to cause
a reset. This bit is cleared by the reset controller for a valid assertion of the RESET pin or
a power-on reset or a write of one to the bit.
1: A glitch was detected on the RESET pin.
0: No glitch was detected on the RESET pin.
SI 0xE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
SSR
SER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
1
1
1
This bit in the MPC5644A MCU has no effect as checkstop reset is not supported.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 16-8. SIU_RSR field description (continued)
Bits
Name
Description
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