NXP Semiconductors MPC5644A, Reference Manual, Page: 37 / 1735

Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 37
1.4.7 FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz crystal
oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation
of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable.
The PLL has the following major features:
• Input clock frequency from 4 MHz to 40 MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to
relock
• 3 modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
• Each of the three modes may be run with a crystal oscillator or an external clock reference
• Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
• Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors
lock status to report loss of lock conditions
• Clock Quality Module
— Detects the quality of the crystal clock and causes interrupt request or system reset if error is
detected
— Detects the quality of the PLL output clock; if error detected, causes system reset or switches
system clock to crystal clock and causes interrupt request
• Programmable interrupt request or system reset on loss of lock
• Self-clocked mode (SCM) operation
1.4.8 SIU
The MPC5644A SIU controls MCU reset configuration, pad configuration, external interrupt, general
purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset
configuration block contains the external pin boot configuration logic. The pad configuration block
controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and discrete
input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring of internal
and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z4
CPU core is via the crossbar switch. The SIU provides the following features:
• System configuration
— MCU reset configuration via external pins
— Pad configuration control for each pad