NXP Semiconductors MPC5644A, Reference Manual, Page: 354 / 1735

Interrupt Controller (INTC)
MPC5644A Microcontroller Reference Manual, Rev. 6
354 Freescale Semiconductor
Figure 15-13. INTC Priority Select Register 0–3 (INTC_PSR0_3)
Figure 15-14. INTC Priority Select Register 482–485 (INTC_PSR482_485)
15.5 Functional description
15.5.1 Interrupt request sources
The INTC has two types of interrupt requests, peripheral and software configurable. The assignments
between the interrupt requests from the modules to the vectors for input to the e200z4 are shown in
Table 15-8 . The Hardware Vector Mode Offset column lists the IRQ-specific offsets when using hardware
vector mode. The Source column shows the C language syntax for the register bit label:
module_register[bit]. Interrupt requests from the same module location are ORed together. The individual
Address: Base + 0x0010 (INTC_IACKR) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 PRI0 0 0 0 0 PRI1
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 PRI2 0 0 0 0 PRI3
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Address: Base + n (INTC_PSR n ); n = 0–485 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 PRI482 0 0 0 0 PRI483
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 PRI484 0 0 0 0 PRI485
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Table 15-7. INTC_PSRn Field Descriptions
Field Description
0–3 Reserved, must be cleared.
4–7
PRI n
Priority select. Selects the priority for corresponding interrupt request.
1111 Priority 15 (highest)
1110 Priority 14
...
0001 Priority 1
0000 Priority 0 (lowest)