Introduction
MPC5644A Microcontroller Reference Manual, Rev. 6
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Freescale Semiconductor
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Vectored interrupt support
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Non-maskable interrupt input
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Critical Interrupt input
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New ‘Wait for Interrupt’ instruction, to be used with new low power modes
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Reservation instructions for implementing read-modify-write accesses
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Signal processing extension (SPE) APU
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Single Precision Floating point (scalar and vector)
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Nexus Class 3+ debug
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Process ID manipulation for the MMU using an external tool
1.4.3
Crossbar Switch (XBAR)
The XBAR multiport crossbar switch supports simultaneous connections between five master ports and
four slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each
master must access a different slave. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other
masters requesting that slave port are stalled until the higher priority master completes its transactions.
Requesting masters are treated with equal priority and are granted access to a slave port in round-robin
fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
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5 master ports
— CPU instruction bus
— CPU data bus
— eDMA
— FlexRay
— External Bus Interface
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4 slave ports
— Flash
— Calibration and EBI bus
— SRAM
— Peripheral bridge
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32-bit internal address, 64-bit internal data paths
1.4.4
eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data movements via 64 programmable channels, with minimal intervention from the
host processor. The hardware micro-architecture includes a DMA engine which performs source and
destination address calculations, and the actual data movement operations, along with an SRAM-based
Summary of Contents for MPC5644A
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