NXP Semiconductors MPC5644A, Reference Manual, Page: 298 / 1735

External Bus Interface (EBI)
MPC5644A Microcontroller Reference Manual, Rev. 6
298 Freescale Semiconductor
14.5.1.9 Support for Dynamic Calibration with up to 4 chip-selects
The EBI contains 4 calibration chip select signals, controlling 4 independent memory banks on an optional
2nd external bus for calibration. See
Section 14.5.2.10, Calibration bus operation ” for more details on
using the calibration bus.
14.5.1.10 Four Write/Byte Enable (WE/BE) Signals
The functionality of the WE[0:3]/BE[0:3] signals depends on the value of the WEBS bit in the
corresponding Base Register. Setting WEBS to 1 configures these pins as BE[0:3], while resetting it to 0
configures them as WE[0:3]. WE[0:3] are asserted only during write accesses, while BE[0:3] is asserted
for both read and write accesses. The timing of the WE[0:3]/BE[0:3] signals remains the same in either
case.
The upper Write/Byte Enable (WE0/BE0) indicates that the upper eight bits of the data bus (DATA[0:7])
contain valid data during a write/read cycle. The upper middle Write/Byte Enable (WE1/BE1) indicates
that the upper middle eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle.
The lower middle Write/Byte Enable (WE2/BE2) indicates that the lower middle eight bits of the data bus
(DATA[16:23]) contain valid data during a write/read cycle. The lower Write/Byte Enable (WE3/BE3)
indicates that the lower eight bits of the data bus (DATA[24:31]) contain valid data during a write/read
cycle.
NOTE
The exception to the preceding WE/BE description is that for 16-bit port
transfers (DBM=1 or PS=1), only the WE[0:1]/BE[0:1] signals are used,
regardless of whether DATA[0:15] or DATA[16:31] are selected (via the
D16_31 bit in the EBI_MCR). This means for the case where DATA[16:31]
are selected, that WE0 indicates that DATA[16:23] contains valid data, and
WE1 indicates that DATA[24:31] contains valid data.
The Write/Byte Enable lines affected in a transaction for a 32-bit port (PS = 0) and a 16-bit port (PS=1)
are shown in
Table 14-11 . Only Big Endian byte ordering is supported by the EBI.