NXP Semiconductors MPC5644A, Reference Manual, Page: 258 / 1735

Memory Protection Unit (MPU)
MPC5644A Microcontroller Reference Manual, Rev. 6
258 Freescale Semiconductor
13.1.2 Modes of operation
The MPU does not support any special modes of operation.
13.2 MPU-to-XBAR slave port mapping
In some of the register field descriptions, references are made to “slave ports”. This is not referring to the
slave ports of the XBAR—it refers instead to the slave ports of the MPU. The mapping is as follows:
13.3 Signal description
The MPU does not include any external signals.
13.4 Memory map and registers
This section provides a detailed description of all MPU registers.
13.4.1 Module memory map
The MPU memory map is shown in Table 13-2 . The address of each register is given as an offset to the
MPU base address. Registers are listed in address order, identified by complete name and mnemonic, and
list the type of accesses allowed.
The MPU registers can be referenced using 32-bit (word) accesses only. Attempted references using
different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example,
a write to a read-only register or a read of a write-only register) generate an error termination.
Table 13-1. MPU-to-XBAR slave port mapping
MPU Slave Port XBAR Slave Port Description
0 2 Device SRAM
1 7 Device Peripheral Bridge (PBRIDGE)
Table 13-2. MPU Memory Map
Offset from
MPU_BASE
(0xFFF1_0000)
Register Location
0x0000 MPU_CESR — MPU control/error status register on page
13-261
0x0004–0x000F Reserved
0x0010 MPU_EAR0 — MPU error address register, slave port 0 on page
13-262
0x0014 MPU_EDR0 — MPU error detail register, slave port 0 on page
13-263
0x0018 MPU_EAR1 — MPU error address register, slave port 1 on page
13-262