NXP Semiconductors MPC5644A, Reference Manual, Page: 200 / 1735

Multi-Layer AHB Crossbar Switch (XBAR)
MPC5644A Microcontroller Reference Manual, Rev. 6
200 Freescale Semiconductor
SGPCR0: Address: XBA 0x0000 (0xFFF0_4010)
SGPCR1: Address: XBA 0x0100 (0xFFF0_4110)
SGPCR2: Address: XBA 0x0200 (0xFFF0_4210)
SGPCR7: Address: XBA 0x0700 (0xFFF0_4710) Access: Supervisor
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
RO
0 0 0 0 0 0 0
HPE7 HPE6
0
HPE4
0 0
HPE1 HPE0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0
ARB
0 0
PCTL
0
PARK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
= not implemented
Figure 9-4. Slave General Purpose Control Register (XBAR_SGPCRn)
Table 9-4. XBAR Slave General Purpose Control Register Field Descriptions
Field Description
0
RO
Read Only
This bit is used to force all of a slave port’s registers to be read only. Once written to 1 it can only be
cleared by hardware reset.
This bit is initialized by hardware reset. The reset value is 0.
0: All this slave port’s registers can be written.
1: All this slave port’s registers are read only and cannot be written (attempted writes have no effect and
result in an error response).
1:7 Reserved
These bits are reserved for future expansion. They read as zero and should be written with zero for
upward compatibility.
8:15
HPEx
High Priority Enable
These bits are used to enable the mX_high_priority inputs for the respective master.
These bits are initialized by hardware reset. The reset value is 0.
0: The mX_high_priority input is disabled on this slave port
1: The mX_high_priority input is enabled on this slave port.
16:21 Reserved
These bits are reserved for future expansion. They are read as zero and should be written with zero for
upward compatibility.