NXP Semiconductors MPC5644A, Reference Manual, Page: 194 / 1735

Multi-Layer AHB Crossbar Switch (XBAR)
MPC5644A Microcontroller Reference Manual, Rev. 6
194 Freescale Semiconductor
9.1.2 Features
The XBAR has the ability to gain control of all the slave ports and prevent any masters from making
accesses to the slave ports. This feature is useful for turning off the clocks to the system and ensuring that
no bus activity will be interrupted.
The XBAR can put each slave port into a low power park mode so that the slave port will not dissipate any
power transitioning address, control or data signals when not being actively accessed by a master port.
Each slave port can also support multiple master priority schemes—the user can dynamically change
master priority levels on a slave port by slave port basis.
The XBAR allows concurrent transactions to occur from any master port to any slave port. It is possible
for all master ports and slave ports to be in use at the same time as a result of independent master requests.
If a slave port is simultaneously requested by more than one master port, arbitration logic will select the
higher priority master and grant it ownership of the slave port. All other masters requesting that slave port
will stalled until the higher priority master completes its transactions.
The XBAR has a 32-bit internal address bus and a 64-bit internal data bus.
9.1.3 Limitations
The XBAR routes bus transactions initiated on the master ports to the appropriate slave ports. There is no
provision included to route transactions initiated on the slave ports to other slave ports or to master ports.
Simply put, the slave ports do not support the bus request/bus grant protocol; the XBAR assumes it is the
sole master of each slave port.
9.1.4 General operation
When a master makes an access to the XBAR the access will be immediately taken by the XBAR. If the
targeted slave port of the access is available then the access will be immediately presented on the slave
port. It is possible to make single clock (zero wait state) accesses through the XBAR. If the targeted slave
port of the access is busy or parked on a different master port the requesting master will simply see wait
Flash Memory Slave S0 —
EBI/Calibration Bus
2
Slave S1 —
SRAM Slave S2 —
Peripheral Bridge Slave S7 —
1
The EBI (External Bus Interface) is connected as a master but is not implemented with a multi-master
mode so it is, in effect, “parked”. Regardless, it must be configured as with other supported masters.
2
The calibration bus is only available on the calibration package.
Table 9-1. Master/Slave mappings
Module
Port
Physical master ID
Type Logical number