NXP Semiconductors MPC5644A, Reference Manual, Page: 173 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 173
— The address and data path modules directly support the two-stage pipelined system bus. The
address path module represents the 1st stage of the bus pipeline (the address phase), while the
data path module implements the second stage of the pipeline (the data phase).
— Program model/channel arbitration: This module implements the first section of eDMA’s
programming model and also the channel arbitration logic. The programming model registers
are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA
interrupt request outputs are also connected to this module (via the control logic).
— Control: This module provides all the control functions for the DMA engine. For data transfers
where the source and destination sizes are equal, the DMA engine performs a series of source
read, destination write operations until the number of bytes specified in the inner minor loop
byte count has been moved.
A minor loop interaction is defined as the number of bytes to transfer ( n bytes) divided by the
transfer size. Transfer size is defined as:
if (SSIZE < DSIZE)
transfer size = destination transfer size (# of bytes)
else
transfer size = source transfer size (# of bytes)
Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR,
BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER,
BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF.
For descriptors where the sizes are not equal, multiple access of the smaller size data are
required for each reference of the larger size. For example, if the source size references 16-bit
data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
• TCD local memory
— Memory controller: This logic implements the required dual-ported controller, handling
accesses from both the DMA engine as well as references from the slave bus. As noted earlier,
in the event of simultaneous accesses, the DMA engine is given priority and the slave
transaction is stalled. The hooks to a BIST controller for the local TCD memory are included
in this module.
— Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array.
8.4.1 eDMA basic data flow
The eDMA transfers data based on a two-deep, nested flow. The basic flow of a data transfer can be
partitioned into three segments. As shown in
Figure 8-24 , the first segment involves the channel service
request. In the diagram, this example uses the assertion of the eDMA peripheral request signal to request
service for channel
n . Channel service request via software and the TCDn.START bit follows the same
basic flow as an eDMA peripheral request. The eDMA peripheral request input signal is registered
internally and then routed to through the DMA engine, first through the control module, then into the
program model/channel arbitration module. In the next cycle, the channel arbitration is performed using
the fixed-priority or round-robin algorithm. After the arbitration is complete, the activated channel number
is sent through the address path and converted into the required address to access the TCD local memory.