NXP Semiconductors MPC5644A, Reference Manual, Page: 1690 / 1735

Nexus Port Controller (NPC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1690 Freescale Semiconductor
37.5.4 Nexus JTAG port sharing
Each of the individual Nexus blocks on the device implements a TAP controller for accessing its registers.
When Nexus has ownership of the TAP, only the block whose NEXUS-ENABLE instruction is loaded has
control of the TAP. This allows the interface to all of these individual TAP controllers to appear to be a
single port from outside the device. If no register is selected as the shift path for a Nexus block, that block
acts like a single-bit shift register, or bypass register.
37.5.5 MCKO and ipg_sync_mcko
MCKO is an output clock to the development tools used for the timing of MSEO and MDO pin functions.
MCKO is derived from the system clock and its frequency is determined by the value of the MCKO_DIV
field in the PCR. Possible operating frequencies include system clock, one-half system clock, one-quarter
system clock, and one-eighth system clock speed.
The NPC also generates an MCKO clock gating control output signal. This output can be used by the
MCKO generation logic to gate the transmission of MCKO when the auxiliary port is enabled but not
transmitting messages. The setting of the MCKO_GT bit inside the PCR determines whether or not MCKO
gating control is active. The MCKO_GT bit resets to a logic 0. In this state gating of MCKO is disabled.
To enable gating of MCKO, the MCKO_GT bit in the PCR is written to a logic 1.
37.5.6 EVTO sharing
The NPC block controls sharing of the EVTO output between all Nexus clients that produce an EVTO
signal. The NPC assumes incoming EVTO signals will be asserted for one system clock period. After
receiving a single clock period of asserted EVTO from any Nexus client, the NPC latches the result, and
drives EVTO for one MCKO period on the following clock. When there is no active MCKO, such as in
disabled mode, the NPC drives EVTO for two system clock periods. EVTO sharing is active as long as the
NPC is not in reset.
16 0 SHIFT-DR DATA_ACCESS TDO becomes active, and outputs current value of
register while new value is shifted in through TDI
31 TCKs
48 1 EXIT1-DR DATA_ACCESS Last bit of current value shifted out TDO. Last bit of
new value shifted in TDI.
49 1 UPDATE-DR DATA_ACCESS Value written to register
50 0 RUN-TEST/IDLE REG_SELECT Controller returned to idle state. It could also return
to SELECT-DR-SCAN to write another register.
Table 37-12. Write to a 32-bit Nexus client register (continued)
Clock TMS IEEE 1149.1 state Nexus state Description