NXP Semiconductors MPC5644A, Reference Manual, Page: 1659 / 1735

JTAG Controller (JTAGC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1659
• 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions as well as
several public and private device-specific instructions (Refer to
Table 36-7 for a list of supported
instructions.)
• Sharing of the TAP with other TAP controllers via ACCESS_AUX_TAP_x instructions
• Test data registers: a bypass register, a boundary scan register, and a device identification register
• TAP controller state machine that controls the operation of the data registers, instruction register
and associated circuitry
36.2.3 Modes of operation
The JTAGC block uses JCOMP and a power-on reset indication as its primary reset signals. Several IEEE
1149.1-2001 defined test modes are supported, as well as a bypass mode.
36.2.3.1 Reset
The JTAGC block is placed in reset when either power-on reset is asserted, JCOMP is negated, or the TMS
input is held high for enough consecutive rising edges of TCK to sequence the TAP controller state
machine into the Test-Logic-Reset state. Holding TMS high for five consecutive rising edges of TCK
guarantees entry into the Test-Logic-Reset state regardless of the current TAP controller state. Asserting
power-on reset or setting JCOMP to a value other than the value required to enable the JTAGC block
results in asynchronous entry into the reset state. While in reset, the following actions occur:
• The TAP controller is forced into the Test-Logic-Reset state, thereby disabling the test logic and
allowing normal operation of the on-chip system logic to continue unhindered.
• The instruction register is loaded with the IDCODE instruction.
36.2.3.2 IEEE 1149.1-2001 defined test modes
The JTAGC block supports several IEEE 1149.1-2001 defined test modes. A test mode is selected by
loading the appropriate instruction into the instruction register while the JTAGC is enabled. Supported test
instructions include EXTEST, HIGHZ, CLAMP, SAMPLE and SAMPLE/PRELOAD. Each instruction
defines the set of data register(s) that may operate and interact with the on-chip system logic while the
instruction is current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the EXTEST,
SAMPLE or SAMPLE/PRELOAD instructions are active. The single-bit bypass register shift stage is
enabled for serial access between TDI and TDO when the HIGHZ, CLAMP or reserved instructions are
active. The functionality of each test mode is explained in more detail in
Section 36.5.4, JTAGC block
instructions .
36.2.3.3 Bypass Mode
When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC block into
bypass mode. While in bypass mode, the single-bit bypass shift register is used to provide a
minimum-length serial path to shift data between TDI and TDO.