NXP Semiconductors MPC5644A, Reference Manual, Page: 1651 / 1735

Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1651
35.4.5 1.2 V voltage regulator controller
A voltage regulator controller is used to source current to the base of an external NPN transistor which
operates as an emitter follower. The 1.2 V supply is produced at the emitter of this transistor with a
maximum DC current of 400 mA (or maximum transient current of 1.2 A).
The regulator output voltage is adjustable using software, to permit the device to center the supply for
maximum transient margin. This adjustment is achieved by writing to field PCM_TRIMR[VDDCTRIM],
which selects one of the 16 voltages available. The reset value of the 4-bit register is “0000”,
corresponding to a typical default voltage of 1.28 V.
The 1.2 V supply can be internally connected internally to a 5 V ADC channel such that the actual voltage
may be read.
35.4.6 1.2 V LVI
A programmable low voltage monitor is connected to the 1.2 V supply. The output of the LVI goes to
logical 1 when the monitored voltage rises above the rising trip point. In case the monitored voltage falls
below the falling trip point, the LVI output goes to logical 0.
The assertion and negation voltages are adjustable via software by writing to field
PCM_TRIMR[LVDCTRIM], which selects one of the 16 voltages available. The reset value of the 4-bit
register is “0000”, corresponding to a rising trip point voltage of 1.16 V. This is the typical default value,
the real default value may vary from sample to sample according to process, temperature and voltage
supply conditions, as detailed in the “PMC Electrical Characteristics” table in the device data sheet.
The LVI 1.2 V can be programmed to trigger power-on reset (enabled by default). If programmed to
generate reset, the monitor is able to hold reset from 1.2 V POR until greater or equal to LVI threshold.
35.4.7 Resets and interrupts
35.4.7.1 Power-on reset
Power-on reset (POR) circuits are present at the following power supplies:
• 3.3 V / 5 V supply of the closest I/O segment (VDDEH1);
• 5 V supply of the PMC block and bandgap (VDDREG);
• 3.3 V regulated supply VDD33;
• 1.2 V regulated supply.
Power-on reset will assert when the voltage levels of the POR power supplies begin to rise. Each POR will
negate when its power supply rises into the specified range. The behavior for each POR during power
supply ramping is shown in
Figure 35-8 .
The dependence between POR and LVI is summarized in Figure 35-9 . As shown, the LVI will reach a
consistent state before the POR actually releases the reset, avoiding false startup condition. This is valid
for each voltage supply monitored by POR/LVI.