NXP Semiconductors MPC5644A, Reference Manual, Page: 1648 / 1735

Power Management Controller (PMC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1648 Freescale Semiconductor
Bandgap is powered by the same supply of the voltage regulator. When voltage regulator supply is
removed (to allow for external powering of 3.3 V and 1.2 V domains), bandgap voltage reference will also
be disabled.
35.4.2 5 V LVI
A programmable low voltage monitor is connected internally to the 5 V supply that feeds the voltage
regulator (VDDREG). The output of the LVI goes to logical 1 when the monitored voltage rises above the
LVI rising trip point. In case the monitored voltage falls below the falling trip point, the LVI output goes
to logical 0.
The assertion and negation voltages are adjustable via software by writing to field
PCM_TRIMR[LVDREGTRIM], which selects one of the 16 voltages available. The reset value of the
4-bit register is “0000”, corresponding to the rising trip point voltage of 4.29 V. This is the typical default
value, the real default value may vary from sample to sample according to process, temperature and
voltage supply conditions, as detailed in the “PMC Electrical Characteristics” table in the device data
sheet.
35.4.3 3.3 V internal voltage regulator
The 3.3 V internal voltage regulator supplies a total DC current of up to 80 mA or a maximum transient
current peak up to 300 mA (if the external decoupling capacitor has the recommended value of
600 nF – 2 µF and ESR < 50 m

).
The regulator is powered by VDDREG and works in the range 4.5 V to 5.5 V, down to 4.0 V with lower
current drive capabilities, and uses the bandgap voltage as absolute reference. The 3.3 V regulator output
is connected to an I/O pad (VRC33) for external capacitance decoupling, then all blocks (except the flash)
that need a 3.3 V supply are connected to the VRC33 pad. The 3.3 V flash power supply is taken at a pad
next to the regulator I/O, which is double bonded together with the VRC33 pad.