NXP Semiconductors MPC5644A, Reference Manual, Page: 158 / 1735

Enhanced Direct Memory Access Controller (eDMA)
MPC5644A Microcontroller Reference Manual, Rev. 6
158 Freescale Semiconductor
8.3.2.10 eDMA Clear Error Register (EDMA_CER)
The EDMA_CER provides a memory-mapped mechanism to clear a given bit in the EDMA_ERH or
EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the EDMA_ERH or EDMA_ERL to be cleared. Setting bit 1 (CERR[0])
provides a global clear function, forcing the entire contents of the EDMA_ERH or EDMA_ERL to be
zeroed, clearing all channel error indicators. Reads of this register return all zeroes.
If bit 0 is set, the CERR command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Offset: EDM 0X001C Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CINT[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-12. eDMA Clear Interrupt Request (EDMA_CIRQR)
Table 8-11. EDMA_CIRQR field descriptions
Field Description
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CINT[0:6]
Clear Interrupt Request
0–32 (64 for eDMA) Clear corresponding bit in EDMA_IRQRH or EDMA_IRQRL.
64–127
Clear all bits in EDMA_IRQRH or EDMA_IRQRL.
Offset: EDM 0x001D Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CERR[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 8-13. eDMA Clear Error Register (EDMA_CER)
Table 8-12. EDMA_CER field descriptions
Field Description
NOP No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CERR[0:6] Clear Error Indicator
0–32 (64 for eDMA) Clear corresponding bit in EDMA_ERH or EDMA_ERL.
64–127
Clear all bits in EDMA_ERH or EDMA_ERL.