NXP Semiconductors MPC5644A, Reference Manual, Page: 1386 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1386 Freescale Semiconductor
Register 1 (eSCI_IFSR1) are cleared. Theses status bits are cleared within one bit time after assertion of
the LRES bit.
31.4.7 Interrupts
This section describes the interrupt sources and interrupt request generation.
31.4.7.1 Interrupt flags and enables
All interrupt sources, interrupt flags, and interrupt enable bits are listed in Table 31-36 . This table indicates
the operational modes, where the interrupt flags can be set by the eSCI module.
31.4.7.2 Interrupt request generation
The eSCI module provides one hardware interrupt request signal to the systems interrupt controller. This
interrupt request signal is asserted if and only if at least one of the interrupt flags and the corresponding
interrupt enables are set to 1. Otherwise the interrupt line is deasserted.
Table 31-36. eSCI Interrupt Flags and Interrupt Enable Bits
Interrupt Source Operational Mode Interrupt Flag Interrupt Enable Bit
Transmitter SCI eSCI_IFSR1[TDRE] eSCI_CR1[TIE]
Transmitter SCI, LIN eSCI_IFSR1[TC] eSCI_CR1[TCIE]
Receiver SCI eSCI_IFSR1[RDRF] eSCI_CR1[RIE]
Receiver SCI eSCI_IFSR1[IDLE] eSCI_CR1[ILIE]
Receiver SCI eSCI_IFSR1[OR] eSCI_CR2[ORIE]
Receiver SCI, LIN eSCI_IFSR1[NF] eSCI_CR2[NFIE]
Receiver SCI, LIN eSCI_IFSR1[FE] eSCI_CR2[FEIE]
Receiver SCI eSCI_IFSR1[PF] eSCI_CR2[PFIE]
Receiver LIN eSCI_IFSR1[BERR] eSCI_CR2[BERRIE]
Receiver LIN eSCI_IFSR2[RXRDY] eSCI_LCR1[RXIE]
Transmitter LIN eSCI_IFSR2[TXRDY] eSCI_LCR1[TXIE]
Receiver LIN eSCI_IFSR2[LWAKE] eSCI_LCR1[WUIE]
Receiver LIN eSCI_IFSR2[STO] eSCI_LCR1[STIE]
Receiver LIN eSCI_IFSR2[PBERR] eSCI_LCR1[PBIE]
Receiver LIN eSCI_IFSR2[CERR] eSCI_LCR1[CIE]
Receiver LIN eSCI_IFSR2[CKERR] eSCI_LCR1[CKIE]
Receiver LIN eSCI_IFSR2[FRC] eSCI_LCR1[FCIE]
Receiver LIN eSCI_IFSR2[UREQ] eSCI_LCR2[URIE]
Transmitter, Receiver LIN eSCI_IFSR2[OVFL] eSCI_LCR2[OFIE]