NXP Semiconductors MPC5644A, Reference Manual, Page: 135 / 1735

e200z4 Core
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 135
7.3.2 Integer unit features
The e200z4 integer units support single cycle execution of most integer instructions:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count leading zero’s function
• 32-bit single cycle barrel shifter for static shifts and rotates
• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divide in <=14 clocks with minimized execution timing
(EU1 only)
• Pipelined 32x32 hardware multiplier array supports 32x32->32 multiply with 2 clock latency, 1
clock throughput
7.3.3 Load/Store unit features
The e200z4 load/store unit supports load, store, and the load multiple / store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle
for load multiple and store multiple word instructions
7.3.4 Cache features
The features of the e200z4 Cache are as follows:
• 8 KB, 2- or 4-way configurable set-associative Instruction Cache
• Linefill Buffer
• 32-bit address bus plus attributes and control
• Supports cache line locking
• Supports Way allocation
• Supports Tag and Data Parity
• Supports Tag and Data Double Error Detection
• Correction/Auto-invalidation capability
7.3.5 MMU features
The features of the MMU are as follows:
• Virtual Memory support
• 32-bit Virtual and Physical Addresses
• 8-bit Process Identifier
• 24-entry fully-associative TLB