NXP Semiconductors MPC5644A, Reference Manual, Page: 1337 / 1735

Enhanced Serial Communication Interface (ESCI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1337
Chapter 31
Enhanced Serial Communication Interface (ESCI)
31.1 Introduction
The ESCI block is an enhanced SCI block with a LIN master interface layer and DMA support. The LIN
master layer complies with the specifications LIN 1.3, LIN 2.0, LIN 2.1, and SAE J2602/1.
31.1.1 Bibliography
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003
• LIN Network for Vehicle Applications, SAE J2602/1, September 1, 2005
• LIN Specification Package Revision 2.1; November 24, 2006
31.1.2 Acronyms and abbreviations
Table 31-1 contains acronyms and abbreviations used in this document.
31.1.3 Glossary
Table 31-1. Acronyms and abbreviations
Term Description
eSCI Enhanced SCI block with LIN support and DMA support
SCI Serial Communications Interface
LIN Local Interconnect Network - A protocol for low-cost automobile networks
LIN PE LIN Protocol Engine, Finite State Machine to control logic of the LIN hardware.
MCLK Module Clock, defined in Section 31.4.3.1, Module clock
TCLK Transmitter Clock, defined in Section 31.4.3.2, Transmitter clock
RCLK Receiver Clock, defined in Section 31.4.3.3, Receiver clock
RSC Receiver Sample Counter, defined in Section 31.4.3.3, Receiver clock
Table 31-2. Glossary
Term Definition
Logic level one The voltage that corresponds to Boolean true (1) state.
Logic level zero The voltage that corresponds to Boolean false (0) state.
Set To set a bit or bits means to establish logic level one on the bit or bits.
Clear To clear a bit or bits means to establish logic level zero on the bit or bits.