NXP Semiconductors MPC5644A, Reference Manual, Page: 1331 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1331
30.9.18.2 Module disable mode
Module disable mode is a module-specific mode that the DSPI can enter to save power. Host CPU can
initiate the module disable mode by setting bit DSPI_MCR[MDIS]. The module disable mode can also be
initiated by hardware.
When the MDIS bit is set, the DSPI negates Clock Enable signal at the next frame boundary. If
implemented, the Clock Enable signal can stop the clock to the non-memory mapped logic. When Clock
Enable is negated, the DSPI is in a dormant state, but the memory mapped registers are still accessible.
Certain read or write operations have a different effect when the DSPI is in the module disable mode.
Reading the RX FIFO Pop Register does not change the state of the RX FIFO. Likewise, writing to the TX
FIFO Push Register does not change the state of the TX FIFO. Clearing either of the FIFOs has no effect
in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPI_MCR have no
effect in the module disable mode. In the module disable mode, all status bits and register flags in the DSPI
return the correct values when read, but writing to them has no effect. Writing to the DSPI_TCR during
module disable mode has no effect. Interrupt and DMA request signals cannot be cleared while in the
module disable mode.
30.10 Initialization/Application information
30.10.1 How to manage DSPI queues
The queues are not part of the DSPI, but the DSPI includes features in support of queue management.
Queues are primarily supported in SPI configuration.
1. When DSPI executes last command word from a queue, the EOQ bit in the command word is set
to indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag DSPI_SR[EOQF] is set.
3. The setting of the EOQ flag disables serial transmission and reception of data, putting the DSPI in
the STOPPED state. The TXRXS bit is cleared to indicate the STOPPED state.
4. The DMA can continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned
to TX FIFO and RX FIFO. This is done by clearing the corresponding DMA enable request bits in
the DMA controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue by reading
DSPI_SR[RXCNT] or by checking DSPI_SR[RFDF] after each read operation of the
DSPI_POPR.
7. Modify DMA descriptor of TX and RX channels for new queues
8. Flush TX FIFO by writing a ‘1’ to bit DSPI_MCR[CLR_TXF]. Flush RX FIFO by writing a ‘1’ to
bit DSPI_MCR[CLR_RXF].
9. Clear transfer count either by setting CTCNT bit in the command word of the first entry in the new
queue or via CPU writing directly to field DSPI_TCR[TCNT].