NXP Semiconductors MPC5644A, Reference Manual, Page: 1322 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1322 Freescale Semiconductor
All request conditions are detected in the SPI configuration and in the CSI configuration. In DSI
configuration only the transfer of current frame complete condition is detected.
30.9.14.1 Transmit FIFO underflow flag (TFUF)
The Transmit FIFO Underflow Flag indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The transmit underflow condition is detected when the TX FIFO of a DSPI operating as a
SPI slave is empty, and a transfer is initiated from an external SPI master.
30.9.14.2 Receive FIFO overflow flag (RFOF)
The Receive FIFO Overflow Flag indicates that an overflow condition in the RX FIFO has occurred, and
that data may be lost. The Receive FIFO Overflow Flag is asserted when the RX FIFO is full, a new frame
has been received in the shift register, and a transfer is initiated.
30.9.15 Modified SPI transfer format
In Modified Transfer Format, the slave peripheral has more time to place data on the SOUT pin before the
DSPI samples the data. In the Modified Transfer Format, the Master samples the incoming data towards
the end of the transfer cycle. For correct operation of the Modified Transfer Format, the user must
thoroughly analyze the SPI link timing budget.
30.9.16 LVDS pad usage
The differential transmitter pad driver LVDS support data rate up to 40 MHz. Figure 30-55 describes the
pad signals interface.
Figure 30-55. LVDS transmitter pad block diagram
Signals lvds_opt0 and lvds_opt1 control the voltage swing on the LVDS pad. These two signals are
controlled by bits SRC[1:0] of the respective SIU_PCR.
Table 30-41 gives the configuration for these bits.
VREF_LVDS
V_IREF_LVDS
LVDS
Transmitter
ipp_do
lvds_obe
pad_n
pad_p
lvds_opt0
lvds_opt1