NXP Semiconductors MPC5644A, Reference Manual, Page: 131 / 1735

e200z4 Core
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 131
Chapter 7
e200z4 Core
This chapter contains an overview of the e200z4 processor core integrated in MPC5644A devices. For
detailed information see the publication
e200z4 Power Architecture
®
Core Reference Manual on
www.freescale.com.
NOTE
There are two differences between the processor core in MPC5644A
devices and the e200z4 documented in the core reference manual.
MPC5644A devices feature a e200z448n3 core with 8 KB of instruction
cache (vs. 4 KB) and 24 MMU entries (vs. 16).
7.1 Overview
The microcontroller’s cost-efficient e200z4 host processor core is built on the Power Architecture
technology and designed specifically for embedded applications.
The e200z4 is a dual-issue, 32-bit Power Architecture compliant design with 64-bit general purpose
registers (GPRs). Power Architecture floating-point instructions are not supported by this core in
hardware, but are trapped and may be emulated by software.
An Embedded Floating-point (EFPU) APU is provided to support real-time single-precision embedded
numerics operations using the general-purpose registers.
A Signal Processing Extension (SPE) APU is provided to support real-time SIMD fixed point and
single-precision, embedded numerics operations using the general-purpose registers. All arithmetic
instructions that execute in the core operate on data in the general purpose registers (GPRs). The GPRs
have been extended to 64-bits in order to support vector instructions defined by the SPE APU. These
instructions operate on a vector pair of 16-bit or 32-bit data types, and deliver vector and scalar results.
In addition to the base Power Architecture instruction set support, the e200z4 core also implements the
VLE (variable-length encoding) technology, providing improved code density.
The e200z4 processor integrates a pair of integer execution units, a branch control unit, instruction fetch
unit and load/store unit, and a multi-ported register file capable of sustaining six read and three write
operations per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching
is performed by the branch unit to allow single-cycle branches in many cases.
The e200z4 contains an 8 KB Instruction Cache as well as a Memory Management Unit. A Nexus Class 3
module is also integrated.
7.2 Features
Features of the e200z4 core include:
• Dual issue, 32-bit Power Architecture compliant CPU
• Implements the VLE APU for reduced code footprint
• In-order execution and retirement