NXP Semiconductors MPC5644A, Reference Manual, Page: 1284 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1284 Freescale Semiconductor
30.8.2.17 DSPI DSI Serialization Source Select Register (DSPI_SSR)
DSPI DSI Serialization Source Select Register provides means to create combined frame for transmission,
containing bits from DSPI_ASDR register and from DSPI_SDR register. Each bit in the DSPI_SSR
register selects corresponding bit to be serialized. When DSPI_DSICR[TXSS] is set, the DSPI_SSR
register value has no effect.
Table 30-24. DSPI_DSICR1 field description
Field Description
0–2 Reserved, should be cleared.
3–7
TSBCNT[0:4]
Timed Serial Bus Operation Count
When TSBC is set, TSBCNT defines the length of the data frame. TSBCNT field valid value is from
3 to 31.
The TSBCNT field selects number of data bits to be shifted out during a transfer in TSB mode. The
number of data bits in the data frame is one more than the value in the TSBCNT field.
8–13 Reserved, should be cleared.
14
DSE1
Data Select Enable1. When TBSC bit is set, the DSE1 bit controls insertion of the zero bit (Data
Select) in the middle of the data frame. The insertion bit position is defined by FMSZ field of
DSPI_CTARn register, selected by DSICTAS field of the DSPI_DSICR register.
0 No Zero bit inserted in the middle of the data frame.
1 Zero bit is inserted at the middle of the data frame. Total number of bits in the data frame is
increased by 1.
15
DSE0
Data Select Enable0. When TBSC bit is set, the DSE0 bit controls insertion of the zero bit (Data
Select) in the beginning of the data frame.
0 No Zero bit inserted in the beginning of the frame.
1 Zero bit is inserted at the beginning of the data frame. Total number of bits in the data frame is
increased by 1.
16–23 Reserved, should be cleared.
24–31
DPCS1_ x
DSI Peripheral Chip Select 0–7
These bits define the PCSs to assert for the second part of the DSI frame when operating in TSB
configuration with dual receiver. The DPCS1 bits select which of the PCS signals to assert during the
second part of the DSI frame. The DPCS1 bits only control the assertions of the PCS signals in TSB
mode.
0 Negate PCS[x]
1 Assert PCS[x]