NXP Semiconductors MPC5644A, Reference Manual, Page: 126 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
126 Freescale Semiconductor
6.4.3 Hardware single precision floating point
The SPE-APU also supports 32-bit IEEE
®
-754 single-precision floating-point formats, and supports
vector and scalar single-precision floating-point operations. Most compiler vendors include libraries that
can emulate floating point functionality. However, by specifying the correct compiler options, the single
precision floating point instructions may be used.
To enable use of hardware floating point the MSR[SPE] field must be set. Refer to Section 6.4.2, Signal
processing extension for register details.
6.4.4 Variable length encoding
In addition to the base Power Architecture instruction set support, the e200z4 core also implements the
VLE (variable-length encoding) APU, providing improved code density. The VLE-APU can be viewed as
a supplement to the existing Power Architecture instruction set that can be conditionally applied to a
portion of, or an entire application for which improved code density is desired.
0
UCLE
SPE
0
WE
CE
0
EE
PR
FP
ME
0
DE
0
IS
DS
0
RI
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Read / Write; Reset - 0x0
Figure 6-5. Machine State Register (MSR)
Table 6-4. MSR field descriptions
Field Description
UCLE User Cache Lock Enable
SPE SPE Available
0: Execution of SPE APU vector instructions is disabled; SPE Unavailable exception taken instead, and
SPE bit is set in ESR.
1: Execution of SPE APU vector instructions is enabled.
WE Wait State (Power management) enable
CE Critical Interrupt Enable
EE External Interrupt Enable
PR Problem State
FP Floating-Point Available
ME Machine Check Enable
DE Debug Interrupt Enable
IS Instruction Address Space
DS Data Address Space
RI Recoverable Interrupt