NXP Semiconductors MPC5644A, Reference Manual, Page: 1253 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1253
• 6 interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF) ‘OR’ Serial frame received while
RX FIFO is full (RFOF). These two interrupts are ORed and given out as FIFO Overrun
interrupt.
— RX FIFO is not empty (RFDF)
— FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the Tx FIFO
is empty)
• Modified transfer formats for communication with slower peripheral devices
• Continuous Serial Communications Clock (SCK)
• Power-saving architectural features
— Support for IPI Green-line Stop Mode
• Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the
Micro Second Channel (MSC) bus downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
• 2 sources of the serialized data:
— eTPU_A and eMIOS output channels
— Memory-mapped register in the DSPI
• Destinations for the deserialized data:
— eTPU_A and eMIOS input channels
— SIU External Interrupt Request inputs
— Memory-mapped register in the DSPI
• Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
• Transfer initiation conditions:
— Continuous
— Edge sensitive hardware triggered
— Change in data
• Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
• Continuous serial communications clock
• Support for parallel and serial chaining of up to 3 DSPI modules
• Parity generation and checking
30.4 DSPI configurations
The DSPI module can operate in three configurations: SPI, DSI and CSI.