NXP Semiconductors MPC5644A, Reference Manual, Page: 1252 / 1735

Deserial Serial Peripheral Interface (DSPI)
MPC5644A Microcontroller Reference Manual, Rev. 6
1252 Freescale Semiconductor
registers. Incoming deserialized data can also be used to trigger external interrupt requests. The channels
and register content are transmitted using a SPI-like protocol. There are three identical DSPI modules
(DSPI_B, DSPI_C and DSPI_D) on the MPC5644A.
The DSPIs have three configurations:
• Serial Peripheral Interface (SPI)—DSPI operates as a SPI with support for queues
• Deserial Serial Interface (DSI)—DSPI serializes eTPU and eMIOS output channels and
deserializes the received data by placing it on the eTPU and eMIOS input channels and as inputs
to the External Interrupt Request sub-block of the SIU
• Combined Serial Interface (CSI)—DSPI operates in both SPI and DSI configurations interleaving
DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers
between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or
through host software.
30.3 Features
The DSPI supports these SPI features:
• Full-duplex, synchronous transfers
• Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins (only in DSPI_B and DSPI_C)
• Master and Slave Mode
• Buffered transmit operation using the TX FIFO with depth of 4 entries
• Buffered receive operation using the RX FIFO with depth of 4 entries
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
• Visibility into the TX and RX FIFOs for ease of debugging
• FIFO Bypass Mode for low-latency updates to SPI queues
• Programmable transfer attributes on a per-frame basis:
— Parameterized number of transfer attribute registers (from 2 to 8)
— Serial clock with programmable polarity and phase
— Various programmable delays:
– PCS to SCK delay
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 32 bits, expandable with software control
— Continuously held chip select capability
• 8 Peripheral Chip Selects, expandable to 256 with external demultiplexer
• Deglitching support for up to 128 Peripheral Chip Selects with external demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)