NXP Semiconductors MPC5644A, Reference Manual, Page: 122 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
122 Freescale Semiconductor
• Consider locking critical performance routines in cache.
The process of enabling the instruction cache involves first invalidating the cache (by setting
L1CSR1[ICINV]) then when invalidation is completed (L1CSR1[ICINV, ICABT] = 0) enabling the cache
(by setting L1CSR1[ICE]).
The L1CSR1 special purpose register is detailed below.For further details of cache configuration registers,
refer to the e200z4 Power Architecture® Core Reference Manual.
0
ICECE
IC
EI
0
IC
ED
T
0
ICUL ICL
O
ICLFC
IC
LOA
ICEA
ICO
R
G
ICABT
IC
INV
ICE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1011; Read/Write; Reset - 0x0
Figure 6-2. L1 Cache Control and Status Register 1 (L1CSR1)
Table 6-2. L1CSR1 field descriptions
Field Description
ICECE Instruction Cache Error Checking Enable
ICEI Instruction Cache Error Injection Enable
ICEDT Instruction Cache Error Detection Type
ICUL Instruction Cache Unable to Lock
ICLO Instruction Cache Lock Overflow
ICLFC Instruction Cache Lock Bits Flash Clear
ICLOA Instruction Cache Lock Overflow Allocate
ICEA Instruction Cache Error Action
ICORG Cache Organization
0 The cache is organized as 64 sets and 2 ways
1 The cache is organized as 32 sets and 4 ways
ICABT Instruction Cache Operation Aborted
Indicates a Cache Invalidate or a Cache Lock Bits Flash Clear operation was aborted prior to
completion. This bit is set by hardware on an aborted condition, and will remain set until cleared by
software writing 0 to this bit location.
ICINV Instruction Cache Invalidate
0: No cache invalidate
1: Cache invalidation operation
When written to a ‘1’, a cache invalidation operation is initiated by hardware. Once complete, this bit is
reset to ‘0’. Writing a ‘1’ while an invalidation operation is in progress will result in an undefined
operation. Writing a ‘0’ to this bit while an invalidation operation is in progress will be ignored. Cache
invalidation operations require approximately 36 cycles to complete. Invalidation occurs regardless of
the enable (ICE) value.
During cache invalidations, the parity check bits are written with a value dependent on the ICEDT
selection. ICEDT should be written with the desired value for subsequent cache operation when ICINV
is set to ‘1’ for proper operation of the cache.