NXP Semiconductors MPC5644A, Reference Manual, Page: 1213 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1213
the block is requesting data to be written into the input buffer. The interrupt request is cleared when the
CPU writes a one in field IBIC of the DECFILTER_MSR, or by the soft reset command.
When in normal, cascade or PSI input mixed modes with enhanced debug enabled (ISEL = 0 and
EDME = 1, DSEL = 0), the input sample data can be read by the CPU when this interrupt request is
asserted. The interrupt is asserted just when a new word of sample data is supplied to the filter sub-block
to be processed. As this filter register is overwritten by the next word of sample data, an input read overrun
event can occur (the DIVR bit in DECFILTER_MSR is asserted) if the interrupt request is not cleared
before, or at the same time as, the new sample arrives to set the interrupt. This DIVR bit is cleared by the
DIVRC bit in the status register DECFILTER_MSR. However, in enhanced debug monitoring, the set
condition has higher priority than the clear. This means that if the set condition and the clear bit IBIC occur
at the same time, the interrupt remains asserted.
26.5.11.3 Output buffer interrupt request
This interrupt is enabled by the register OBIE in the DECFILTER_MCR and is asserted only when DSEL
= 0. This request is also indicated in the field OBIF of the DECFILTER_MSR.
When in standalone mode, the output buffer can be read by the CPU with the DMA disabled. The output
buffer interrupt request is asserted when the output buffer receives a new result from the filter sub-block.
This means the block is requesting data to be read by the CPU.
The output buffer interrupt request can also be asserted due to an integrator result being ready, as flagged
by the DECFILTER_MXSR bit SDF, when the DECFILTER_MCR bit SDIE = 1. Note that both the filter
output and integrator share the same interrupt source.
This interrupt request is cleared when a one is written in the bit OBIC and/or bit SDFC of the
DECFILTER_MXSR, or by the soft reset command.
26.5.12 DMA requests description
The DMA function for integrator result, input and output buffers is enabled using DSEL = 1 in the
DECFILTER_MCR.
26.5.12.1 Input Buffer DMA request
This DMA request is enabled by the ISEL and DSEL bits in the DECFILTER_MCR.
When in standalone mode, the input buffer can be written by the DMA. The input buffer DMA request is
asserted when the input buffer is available to receive a conversion sample (it is not holding a word of data).
This DMA request is cleared when an input data word is written in the input buffer. Therefore, the DMA
request is always cleared before it is asserted again.
When in normal mode with enhanced debug enabled (ISEL = 0 and EDME = 1, DSEL = 1), the input
sample data can be read by the DMA when this DMA request is asserted. The request is asserted when a
new word of sample data is written into the input buffer to be processed. As this filter register is
overwritten by the next word of sample data, a DMA read overrun event can occur (the DIVR bit in
DECFILTER_MSR is asserted) if the DMA request is not cleared before, or at the same time as, a new