NXP Semiconductors MPC5644A, Reference Manual, Page: 1197 / 1735

Decimation Filter
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 1197
26.4.2.10 Decimation Filter Final Integration Value Register
(DECFILTER_FINTVAL)
NOTE
If the DEFILTER_MXCR bit SSAT = 1, the integration sum is saturated, so
that if the accumulation overflows DECFILTER_FINTVAL holds the value
0xFFFFFFFF for absolute integration (SSIG = 0), or values 0x7FFFFFFF
(positive saturation) and 0x80000000 (negative saturation) for signaled
integration (SSIG = 1).
If SSAT = 0, DECFILTER_FINTVAL holds the integration sum modulo 2
17
(considering the 15-bit fractional part).
Address: DECFILTE 0x0E0 Access: User read only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R SUM_VALUE[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SUM_VALUE[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-11. Decimation Filter Final Integration Value Register (DECFILTER_FINTVAL)
Table 26-23. DECFILTER_FINTVAL Register Field Descriptions
Field Description
0–31
SUM_VALUE
[31:0]
Integration Sum Value. The SUM_VALUE[31:0] field holds the sum of filtered output values. The
17 most significant bits hold the integer part, and the 15 least significant ones the fractional part
of the integration value. The control of the integration sum and update of this register is
determined by the register DECFILTER_MXCR (see
Section 26.4.2.3, Decimation Filter Module
Extended Configuration Register (DECFILTER_MXCR) ”). The register is updated only upon an
integration output request.
SUM_VALUE should be taken as an unsigned number when the integrator is configured for
absolute operation (DECFILTER_MXCR bit SSIG = 0), and a two’s complement signed number
otherwise.