NXP Semiconductors MPC5644A, Reference Manual, Page: 119 / 1735

Device Performance Optimization
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 119
Further details of the BUCSR can be found in the e200z4 Power Architecture® Core Reference Manual.
6.3.2 Frequency-modulated PLL
6.3.2.1 Description
The frequency-modulated phase-locked loop (FMPLL) allows the user to generate high speed system
clocks from a crystal oscillator or external clock generator. Further, the FMPLL supports programmable
frequency modulation of the system clock. This module is typically configured early in the initialization
code to ensure satisfactory performance levels are achieved.
6.3.2.2 Recommended configuration
The default operating frequency of the MPC5644A device is 2 to 3 times the crystal reference frequency
depending on the state of the PLL configuration pins as reset negates. Typically, the system frequency is
increased shortly after reset negates to provide acceptable performance.
Chapter 17, Frequency-modulated
phase locked loop (FMPLL) , provides details on how the frequency-modulated phase-locked loop should
Table 6-1. BUCSR field descriptions
Field Description
BBFI Branch target buffer flash invalidate
When set, BBFI flash clears the valid bit of all BTB entries; clearing occurs regardless of the value of
the enable bit (BPEN).
Note : BBFI is always read as 0.
BALLOC Branch Target Buffer Allocation Control
00: Branch Target Buffer allocation for all branches is enabled.
01: Branch Target Buffer allocation is disabled for backward branches.
10: Branch Target Buffer allocation is disabled for forward branches.
11: Branch Target Buffer allocation is disabled for both branch directions.
This field controls BTB allocation for branch acceleration when BPEN = 1. Note that BTB hits are not
affected by the settings of this field. Note that for branches with AA = ‘1’, the MSB of the displacement
field is still used to indicate forward/backward, even though the branch is absolute.
BPRED Branch Prediction Control (Static)
00: Branch predicted taken on BTB miss for all branches.
01: Branch predicted taken on BTB miss only for forward branches.
10: Branch predicted taken on BTB miss only for backward branches.
11: Branch predicted not taken on BTB miss for both branch directions.
This field controls operation of static prediction mechanism on a BTB miss. Unless disabled, fetching
of the predicted target location will be performed for branch acceleration. BPRED operates
independently of BPEN, and with a BPEN setting of 0, will be used to perform static prediction of all
unresolved branches.
Note that BTB hits are not affected by the settings of this field. Note that for certain applications, setting
BPRED to a non-default value may result in improved performance.
BPEN Branch target buffer (BTB) enable
0: BTB prediction disabled. No hits are generated from the BTB and no new entries are allocated.
Entries are not automatically invalidated when BPEN is cleared; BBFI controls entry invalidation.
1: BTB prediction enabled (enables BTB to predict branches).