NXP Semiconductors MPC5644A, Reference Manual, Page: 109 / 1735

Operating Modes and Clocking
MPC5644A Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 109
VCO range supported) with the /4 output divider to achieve 120 MHz system clock. The VCO/6
(80 MHz) output from PLL(PHI1) would be selected as the clock source for FlexRay by
configuration of the MCF[CLKSEL] control bit on the FlexRay module.
5.3.3.4 Support for CAN interface operation
The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is
always derived from the system clock. This clock domain includes the message buffer logic.
The source for the second clock domain can be either the system clock or a direct feed from the crystal
oscillator pin. The logic in the second clock domain controls the CAN interface pins. Field
FlexCAN_CR[CLKSRC] selects between the system clock and the on-chip MHz oscillator clock as the
clock source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on
the CAN bus.
Software can gate both clocks by writing to FlexCAN_MCR[MDIS] or by writing to the SIU_HLT
register.
5.3.4 FMPLL modes of operation
Upon reset, the FMPLL operational mode is bypass with PLL running, and the source of the reference
clock, either the crystal oscillator or external clock, is determined by the state of the CLKCFG[] bit of the
FMPLL_ESYNCR1 register. The reset state of this bit comes from an external signal to the module
connected to a package pin called PLLREF. After reset, a different operational mode can be selected by
writing to FMPLL_ESYNCR1[CLKCFG]. The available modes are specified in
Table 5-1 .
The reset state of the FMPLL is enabled with the pre-divider set such that it inhibits the clock to the PLL
Phase detector, making the VCO run within its free-running frequency range of 25 MHz to 125 MHz,
unconnected from the system clock (since bypass is the default mode at reset). If using crystal reference,
Table 5-1. Clock Mode Selection
CLKCFG[]
(Bypass)
CLKCFG[1]
1
(PLL enable)
1
CLKCFG[1] is not writable to zero while CLKCFG[]=1.
CLKCFG[]
2
(Clock source)
2
The reset state of this bit is determined by the logical state applied to the PLLREF pin.
Clock mode
0 0 0 Bypass mode with external reference and PLL off
0 0 1 Bypass mode with crystal reference and PLL off
0 1 0 Bypass mode with external reference and PLL running
0 1 1 Bypass mode with crystal reference and PLL running
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Normal mode with external reference
1 1 1 Normal mode with crystal reference