NXP Semiconductors MPC5644A, Reference Manual, Page: 1008 / 1735

Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1008 Freescale Semiconductor
If the command message transmission is aborted, the EQADC will complete the abort procedure
before halting future command transfers from any CFIFO. The message of the CFIFO that caused
the abort of the previous serial transmission will only be transmitted after debug mode is exited.
• Command/Null message transfer through serial interface was aborted but next serial transmission
did not start.
If the debug mode entry request is detected between the time a previous serial transmission was
aborted and the start of the next transmission, the EQADC will complete the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission will only be transmitted after debug mode is exited.
25.3.4 Stop mode
Upon a stop mode entry request detection, the EQADC progressively halts its operations until it reaches a
static, stable state from which it can recover when returning to Normal mode. EQADC then asserts an
acknowledge signal, indicating that it is static and that the clock input can be stopped. In stop mode, the
free running clock (FCK) output to external device will stop during its low phase if the EQADC SSI is
enabled, and no hardware trigger events will be captured. The latter implies that, as long as the system
clock is running, CFIFOs can still be triggered using software triggers, since no scheme is implemented to
write-protect registers during stop mode.
If at the time the stop mode entry request is detected, there are commands in the on-chip CBuffers that
were already under execution, these commands will be completed but the generated results, if any, will not
be sent to the RFIFOs until stop mode is exited. Commands whose execution has not started will not be
executed until stop mode is exited.
After these remaining commands are executed, the clock input to the ADCs is stopped. The ADC clock
stops during its low phase. The time base counter will only stop after all on-chip ADCs cease executing
commands. Only then, the stop acknowledge signal is asserted. When exiting stop mode, the EQADC
relies on the CFIFO operation modes and on the CFIFO status to determine the next command entry to
transfer.
The EQADC internal behavior after the stop mode entry request is detected differs depending on the status
of the command transfer.
• No command transfer is in progress
The EQADC immediately halts future command transfers from any CFIFO.
If a null message is being transmitted, EQADC will complete the transmission before halting future
command transfers. If valid data (conversion result or data read from an ADC register) is received
at the end of the transmission, it will not be sent to an RFIFO until stop mode is exited.
If the null message transmission is aborted, the EQADC will complete the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission will only be transmitted after stop mode is exited.
• Command transfer is in progress
EQADC will complete the transfer and update CFIFO status before halting future command
transfers from any CFIFO. Command transfers to the internal CBuffers are considered completed
when a command is written to the buffers.