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Enhanced Queued Analog-to-Digital Converter (EQADC)
MPC5644A Microcontroller Reference Manual, Rev. 6
1006
Freescale Semiconductor
— Supports configurable digital filter
— Supports controls to bypass the trigger digital filters
•
Two Triggers operation mode for queue0
— Additional internal trigger (not filtered) called Advance trigger that is used to enable the
external trigger of queue0 and to control the loop behavior of CFIFO0
•
Supports 4 to 8 external 8-to-1 muxes which can expand the input channel number from 40 to 96
•
Upgrades the functionality provided by the QADC
25.3
Modes of operation
This section describes the operation modes of the EQADC.
25.3.1
Normal mode
This is the default operational mode when the EQADC is not in streaming mode or background debug or
stop mode.
25.3.2
Streaming mode
This mode is characterized by two main aspects: the abort action by CFIFO0 in any current conversion
process started from another queue, and the loop behavior of the CFIFO0.
In some applications, there may be sequences of identical commands each spaced only by a few
microseconds. To reduce the DMA data transfer, in this mode a short command queue can be stored in
CFIFO0 and repeatedly be executed based on a timed trigger, but advance to the next (repeating) sequence
of commands based on another device’s internal trigger.
The CFIFO0 delivers commands to the ADC as before, but those commands are not ‘invalidated’ after they
are sent (in fact, they are ‘invalidated’ only because the Transfer Next Data Pointer has moved on). When
it encounters these repeated commands the CFIFO0 only fills once, using the DMA as usual, until either
it is full or a command with End-of-Queue is encountered. Thereafter the sub-queue repeats/wraps. The
number of commands loaded is unaffected by the delivery of commands once the streaming mode is
configured, since no commands loaded are invalidated even if sent before all the queue is loaded.
The number of entries in the CFIFO0 is extended to eight (configurable). This is to facilitate the targeted
applications. The repeating subqueue must be contained within the eight CFIFO0 entries.
To maintain compatibility, CFIFO0 by default operates as it does before, without streaming and with four
entries. Streaming, and additional entries, can be enabled independently.
Streaming mode is selected as another mode for queue 0 using the configuration bits in the
EQADC_CFCR register. Streaming mode makes use of an additional bit in the Conversion Command
Word (CCW); this bit is called ‘Repeat’. The purpose of this bit is to mark in the command queue, where
to start a repeating sequence.
Streaming mode requires two trigger inputs. The standard queue 0 trigger, in this mode referred to as
‘Repeat Trigger’ and a second internal trigger input to the eQADC called ‘Advance’ trigger.
Summary of Contents for MPC5644A
Page 2: ...MPC5644A Microcontroller Reference Manual Rev 6 2 Freescale Semiconductor...
Page 24: ...MPC5644A Microcontroller Reference Manual Rev 6 24 Freescale Semiconductor...
Page 26: ...MPC5644A Microcontroller Reference Manual Rev 6 26 Freescale Semiconductor...
Page 52: ...Introduction MPC5644A Microcontroller Reference Manual Rev 6 52 Freescale Semiconductor...
Page 56: ...Memory Map MPC5644A Microcontroller Reference Manual Rev 6 56 Freescale Semiconductor...
Page 1228: ...Decimation Filter MPC5644A Microcontroller Reference Manual Rev 6 1228 Freescale Semiconductor...
Page 1440: ...FlexCAN Module MPC5644A Microcontroller Reference Manual Rev 6 1440 Freescale Semiconductor...