NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
956 Freescale Semiconductor
35.10 Initialization/application information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS
2. Load the appropriate instruction for the test or action to be performed.
111 1101 LSRL Select
(factory test use only)
111 1110 Enable_OnCE
111 1111 Bypass
Table 35-4. e200z0 OnCE register addressing (continued)
RS[0:6] Register selected