NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 885
The bank1 temporary holding register effectively operates like a single page buffer.
30.8.10 Read-while-write functionality
The platform flash memory controller supports various programmable responses for read accesses while
the flash memory is busy performing a write (program) or erase operation. For all situations, the platform
flash memory controller uses the state of the flash memory array’s MCR[DONE] output to determine if it
is busy performing some type of high voltage operation, namely, if MCR[DONE] = 0, the array is busy.
Specifically, two 3-bit read-while-write (BK n _RWWC) control register fields define the platform flash
memory controller’s response to these types of access sequences. The following unique responses are
defined by the BK
n _RWWC setting: one that immediately reports an error on an attempted read and four
settings that support various stall-while-write capabilities. Consider the details of these settings.
• BK n _RWWC = 0b111
This defines the basic stall-while-write capability and represents the default reset setting. For this
mode, the platform flash memory controller module simply stalls any read reference until the flash
memory has completed its program/erase operation. If a read access arrives while the array is busy
or if MCR[DONE] goes low while a read is still in progress, the AHB data phase is stalled and the
read access address is saved. Once the array has completed its program/erase operation, the
platform flash memory controller uses the saved address and attribute information to create a
pseudo address phase cycle to retry the read reference and sends the registered information to the
array. Once the retried address phase is complete, the read is processed normally and once the data
is valid, it is forwarded to the AHB bus to terminate the system bus transfer.
• BK n _RWWC = 0b110
This setting is similar to the basic stall-while-write capability provided when
BK
n _RWWC = 0b111 with the added ability to generate a notification interrupt if a read arrives
while the array is busy with a program/erase operation. There are two notification interrupts, one
for each bank (see
Chapter 18, Interrupt Controller (INTC) ).
• BK n _RWWC = 0b101
Again, this setting provides the basic stall-while-write capability with the added ability to abort any
program/erase operation if a read access is initiated. For this setting, the read request is captured
and retried as described for the basic stall-while-write, plus the program/erase operation is aborted
by the platform flash memory controller. For this setting, no notification interrupts are generated.
• BK n _RWWC = 0b100
This setting provides the basic stall-while-write capability with the ability to abort any
program/erase operation if a read access is initiated plus the generation of an abort notification
interrupt. For this setting, the read request is captured and retried as described for the basic
stall-while-write, the program/erase operation is aborted by the platform flash memory controller
and an abort notification interrupt generated. There are two abort notification interrupts, one for
each bank.
As detailed above, a total of four interrupt requests are associated with the stall-while-write functionality.
These interrupt requests are captured as part of ECSM’s interrupt register and logically summed together
to form a single request to the interrupt controller.