NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 27 Timers
MPC5606BK Microcontroller Reference Manual, Rev. 2
664 Freescale Semiconductor
27.4.3.2.7 eMIOS UC Counter Register (EMIOSCNT[n])
The EMIOSCNT[n] register contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOSCNT[n] register is read/write. For all others modes, the EMIOSCNT[n] is a
read-only register. When entering some operation modes, this register is automatically cleared (refer to
Section 27.4.4.1.1, UC modes of operation , for details).
Depending on the channel configuration it may have an internal counter or not. It means that if at least one
mode that requires the counter is implemented, then the counter is present; otherwise it is absent.
Table 27-16. EMIOSA[n], EMIOSB[n] and EMIOSALTA[n] values assignment
Operation mode
Register access
write read write read alt write alt read
GPIO A1, A2 A1 B1,B2 B1 A2 A2
SAIC
1
— A2 B2 B2 — —
SAOC
1
1
In these modes, the register EMIOSB[n] is not used, but B2 can be accessed.
A2 A1 B2 B2 — —
IPWM — A2 — B1 — —
IPM — A2 — B1 — —
DAOC A2 A1 B2 B1 — —
MC
1
A2 A1 B2 B2 — —
OPWMT A1 A1 B2 B1 A2 A2
MCB
1
A2 A1 B2 B2 — —
OPWFMB A2 A1 B2 B1 — —
OPWMCB A2 A1 B2 B1 — —
OPWMB A2 A1 B2 B1 — —
Address: UC[n] base a 0x08
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
1
1
In GPIO mode or Freeze action, this register is writable.
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R C
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-14. eMIOS UC Counter Register (EMIOSCNT[n])