NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 25 FlexCAN
MPC5606BK Microcontroller Reference Manual, Rev. 2
572 Freescale Semiconductor
25.4.4.9 Interrupt Masks 2 (IMASK2) register
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (i.e., when the corresponding IFLAG2 bit is set).
ERR_INT Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16-21) is set. If the corresponding mask bit
in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to 1.Writing 0 has no effect.
0 No such occurrence
1 Indicates setting of any Error Bit in the Error and Status Register
Table 25-15. Fault confinement state
Value Meaning
00 Error Active
01 Error Passive
1X Bus Off
Offset: 0x0024 Access: Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BUF
63M
BUF
62M BUF
61M BUF
60M BUF
59M BUF
58M BUF
57M BUF
56M BUF
55M BUF
54M BUF
53M BUF
52M BUF
51M BUF
50M BUF
49M BUF
48M
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BUF
47M
BUF
46M BUF
45M BUF
44M BUF
43M BUF
42M BUF
41M BUF
40M BUF
39M BUF
38M BUF
37M BUF
36M BUF
35M BUF
34M BUF
33M BUF
32M
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 25-11. Interrupt Masks 2 (IMASK2) register
Table 25-16. MASK2 field descriptions
Field Description
BUF n M Buffer MB
n
Mask
Each bit enables or disables the respective FlexCAN Message Buffer (MB32 to MB63)
Interrupt.
0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the IMASK2 register can assert or negate an interrupt
request, if the corresponding IFLAG2 bit is set.
Table 25-14. ESR field descriptions (continued)
Field Description