NXP Semiconductors MPC5605BK, Reference Manual

Page: 339 / 964

Chapter 18 Interrupt Controller (INTC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 339
(INTC_PSR0_3–INTC_PSR232_233) must be selected to be at or lower than the priority of the ISR that
cleared their flag bits. Otherwise, those flag bits can cause the interrupt request to the processor to assert.
Furthermore, the clearing of these other flag bits also has the same timing relationship to the writing to
INTC_SSCIR0_3–INTC_SSCIR4_7 as the clearing of the flag bit that caused the present ISR to be
executed (see
Section 18.6.3.1.2, End of interrupt exception handler ).
A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time,
regardless of the peripheral interrupt request’s PRI
x value in INTC_PSR x _ x .
18.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even know how
deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not
memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either
INTC_CPR.
The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo