NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 18 Interrupt Controller (INTC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
332 Freescale Semiconductor
Figure 18-12. Hardware vector mode handshaking timing diagram
18.7 Initialization/application information
18.7.1 Initialization flow
After exiting reset, all of the PRI n fields in INTC priority select registers (INTC_PSR0–INTC_PSR233)
will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will
prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the
peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for
allowing the peripheral and software settable interrupt requests to cause an interrupt request to the
processor is:
interrupt_request_initialization:
configure VTES and HVEN in INTC_MCR
configure VTBA in INTC_IACKR
raise the PRI n fields in INTC_PSR
n
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR to zero
enable processor recognition of interrupts
18.7.2 Interrupt exception handler
These example interrupt exception handlers use Power Architecture assembly code.
0 108
0 1 0
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
Interrupt acknowledge
Read INTC_IACKR
Write INTC_EOIR
INTVEC in INTC_IACKR
PRI in INTC_CPR
Peripheral interrupt request 100
0 108