NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 15 e200z0h Core
MPC5606BK Microcontroller Reference Manual, Rev. 2
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• 32-bit mask unit for data masking and insertion
• Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing
• 8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32

32 multiply (early out)
15.4.3 Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple instructions:
• 32-bit effective address adder for data memory address calculations
• Pipelined operation supports throughput of one load or store operation per cycle
• 32-bit interface to memory (dedicated memory interface on e200z0h)
15.4.4 e200z0h system bus features
The features of the e200z0h system bus interface are as follows:
• Independent instruction and data buses
• AMBA
1
AHB
2
Lite Rev 2.0 specification with support for ARM v6 AMBA extensions
— Exclusive access monitor
— Byte lane strobes
— Cache allocate support
• 32-bit address bus plus attributes and control on each bus
• 32-bit read data bus for instruction interface
• Separate uni-directional 32-bit read data bus and 32-bit write data bus for data interface
• Overlapped, in-order accesses
15.5 Core registers and programmer’s model
This section describes the registers implemented in the e200z0h cores. It includes an overview of registers
defined by the Power Architecture platform, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in the Power Architecture specification.
The Power Architecture defines register-to-register operations for all computational instructions. Source
data for these instructions are accessed from the on-chip registers or are provided as immediate values
embedded in the opcode. The three-register instruction format allows specification of a target register
distinct from the two source registers, thus preserving the original data for use by other instructions. Data
is transferred between memory and registers with explicit load and store instructions only.
Figure 15-2 , and Figure 15-1 show the e200 register set, including the registers that are accessible while
in supervisor mode, and the registers that are accessible in user mode. The number to the right of the
special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register
(for example, the integer exception register (XER) is SPR 1).
1. Advanced Microcontroller Bus Architecture
2. Advanced High Performance Bus