NXP Semiconductors MPC5605BK, Reference Manual

Page: 217 / 964

Chapter 12 Wakeup Unit (WKPU)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 217
NOTE
Reserved registers will read as 0, writes will have no effect. If
SSCM_ERROR[RAE] is enabled, a transfer error will be issued when
trying to access completely reserved register space.
12.4.2 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
0x30 Wakeup/Interrupt Filter Enable Register (WIFER) on page 221
0x34 Wakeup/Interrupt Pullup Enable Register (WIPUER) on page 222
Offset: 0x00 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
NIF0
NO
VF0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 12-2. NMI Status Flag Register (NSR)
Table 12-3. NSR field descriptions
Field Description
NIF0 NMI Status Flag
If enabled (NREE0 or NFEE0 set), NIF0 causes an interrupt request.
1 An event as defined by NREE0 and NFEE0 has occurred
0 No event has occurred on the pad
NOVF0 NMI Overrun Status Flag
It will be a copy of the current NIF0 value whenever an NMI event occurs, thereby indicating to the
software that an NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0
set), NOVF0 causes an interrupt request.
1 An overrun has occurred on NMI input
0 No overrun has occurred on NMI input
Table 12-2. WKPU memory map (continued)
Base address: 0xC3F9_4000
Address offset Register name Location