External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
12-29
The termination phase is where the cycle is terminated by the assertion of either TA (normal termination)
or TEA (termination with error). Termination is discussed in detail in
Section 12.4.2.9, “Termination
.”
12.4.2.4
Single-Beat Transfer
The flow and timing diagrams in this section are for the EBI configured as single master mode. Therefore,
arbitration is not needed and is not shown in these diagrams. See
Section 12.4.2.10, “Bus Operation in
,” to read how the flow and timing diagrams change for external master mode.
12.4.2.4.1
Single-Beat Read Flow
The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.
Figure 12-9. Basic Flow Diagram of a Single-Beat Read Cycle
Yes
No
Receives address
Asserts transfer start (TS)
drives address and attributes
Master (EBI)
Drives data
Asserts transfer
acknowledge (TA)
Asserts transfer
acknowledge (TA)
Receives data
Slave
CS access
?
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
