NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-21
12.4 Functional Description
12.4.1 External Bus Interface Features
12.4.1.1 32-Bit Address Bus with Transfer Size Indication
The transfer size for an external transaction is indicated by the TSIZ[0:1] signals during the clock where
address is valid. Valid transaction sizes are 8, 16, and 32 bits. In the 416 and 496 BGA packaged devices,
only 24 or 26 address lines are pinned out externally, but a full 32-bit decode is done internally to determine
the target of the transaction and whether to assert a chip select.
12.4.1.2 32-Bit Data Bus
The entire 32-bit data bus is available for both external memory accesses and transactions involving an
external master in the 416 and 496 BGA packaged devices.
12.4.1.3 16-Bit Data Bus
A 16-bit data bus mode is available via the DBM bit in EBI_MCR. See Section 12.1.4.5, “16-Bit Data Bus
Mode .”
12.4.1.4 Support for External Master Accesses to Internal Addresses
The EBI allows an external master to access internal address space when the EBI is configured for external
master mode in the EBI_MCR. External master operations are described in detail in
Section 12.4.2.10,
“Bus Operation in External Master Mode .”
29–30
BSCY
[0:1]
Burst beats length in clocks. This field determines the number of wait states (external bus cycles) inserted in all burst
beats except the first, when the memory controller starts handling the external memory access and thus is using
SCY[0:3] to determine the length of the first beat.
• Total memory access length for each beat:
• Total cycle length (including the TS cycle):
Note: The number of beats (4, 8, 16) is determined by BL and PS bits in the base register.
00 0-clock cycle wait states (1 clock per data beat)
01 1-clock cycle wait states (2 clocks per data beat)
10 2-clock cycle wait states (3 clocks per data beat)
11 3-clock cycle wait states (4 clocks per data beat)
31 Reserved.
Table 12-11. EBI_OR n and EBI_CAL_OR n Field Descriptions (continued)
Field Description
(1 + BSCY) external clock cycles
(2 + SCY) + [(number of beats – 1) x (BSCY + 1)]