NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-9
6.3.1 Register Descriptions
The register figures use the following notational conventions in this section:
Base + 0x0018 SIU_DIRER DMA/interrupt request enable register 32
Base + 0x001C SIU_DIRSR DMA/interrupt request select register 32
Base + 0x0020 SIU_OSR Overrun status register 32
Base + 0x0024 SIU_ORER Overrun request enable register 32
Base + 0x0028 SIU_IREER IRQ rising-edge event enable register 32
Base + 0x002C SIU_IFEER IRQ falling-edge event enable register 32
Base + 0x0030 SIU_IDFR IRQ digital filter register 32
Base + (0x0034–0x003F) Reserved
Base + (0x0040–0x020C) SIU_PCR0–SIU_PCR230 Pad configuration registers 0–230 16
Base + (0x020E–0x05FF) Reserved
Base + (0x0600–0x06D5) SIU_GPDO0–SIU_GPDO213 GPIO pin data output registers 0–213 8
Base + (0x06D6–0x07FF) Reserved
Base + (0x0800–0x08D5) SIU_GPDI0–SIU_GPDI213 GPIO pin data input registers 0–213 8
Base + (0x08D6–0x08FF) Reserved
Base + (0x0900–0x0903) SIU_ETISR eQADC trigger input select register 32
Base + (0x0904–0x0907) SIU_EIISR External IRQ input select register 32
Base + (0x0908–0x090B) SIU_DISR DSPI input select register 32
Base + (0x090C–0x097F) Reserved
Base + 0x0980 SIU_CCR Chip configuration register 32
Base + 0x0984 SIU_ECCR External clock control register 32
Base + 0x0988 SIU_CARH Compare A high register 32
Base + 0x098C SIU_CARL Compare A low register 32
Base + 0x0990 SIU_CBRH Compare B high register 32
Base + 0x0994 SIU_CBRL Compare B low register 32
Base + (0x0998–0x09FF) Reserved
w1c Write 1 to clear the bit to 0.
— Not applicable.
Reserved or unimplemented bit.
U Bit value is uninitialized upon reset.
u Bit value is unchanged upon reset.
Table 6-5. SIU Register Address Map
Address Name Description Bits