NXP Semiconductors MKW01Z128, Reference Manual, Page: 811 / 884

GPIOx_PDDR field descriptions
Field Description
PDD Port Data Direction
Configures individual port pins for input or output.
0 Pin is configured as general-purpose input, for the GPIO function.
1 Pin is configured as general-purpose output, for the GPIO function.
34.3 FGPIO memory map and register definition
The GPIO registers are also aliased to the IOPORT interface on the Cortex-M0+ from
address 0xF800_0000.
Accesses via the IOPORT interface occur in parallel with any instruction fetches and will
therefore complete in a single cycle. This aliased Fast GPIO memory map is called
FGPIO.
Any read or write access to the FGPIO memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states, except
error accesses which complete with one wait state.
NOTE
For simplicity, each FGPIO port's registers appear with the
same width of 32 bits, corresponding to 32 pins. The actual
number of pins per port (and therefore the number of usable
control bits per port register) is chip-specific. Refer to the Chip
Configuration chapter to see the exact control bits for the non-
identical port instance.
FGPIO memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F800_0000 Port Data Output Register (FGPIOA_PDOR) 32 R/W 0000_0000h 34.3.1/682
F800_0004 Port Set Output Register (FGPIOA_PSOR) 32
W
(always
reads 0)
0000_0000h 34.3.2/682
F800_0008 Port Clear Output Register (FGPIOA_PCOR) 32
W
(always
reads 0)
0000_0000h 34.3.3/683
F800_000C Port Toggle Output Register (FGPIOA_PTOR) 32
W
(always
reads 0)
0000_0000h 34.3.4/683
Table continues on the next page...
FGPIO memory map and register definition
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
680 Freescale Semiconductor, Inc.