NXP Semiconductors MKW01Z128, Reference Manual

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33.4.3.2.1 Idle-line wakeup
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a full character time
of the idle-line level. The UART_C1[M] control field selects 8-bit or 9-bit data mode and
UART_BDH[SBNS] selects 1-bit or 2-bit stop bit number that determines how many bit
times of idle are needed to constitute a full character time, 10 or 11 or 12 bit times
because of the start and stop bits.
When UARTI_C2[RWU] is 1 and UART_S2[RWUID] is 0, the idle condition that wakes
up the receiver does not set UART_S1[IDLE]. The receiver wakes up and waits for the
first data character of the next message that sets UART_S1[RDRF] and generates an
interrupt, if enabled. When UART_S2[RWUID] is 1, any idle condition sets
UART_S1[IDLE] flag and generates an interrupt if enabled, regardless of whether
UART_C2[RWU] is 0 or 1.
The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle
line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the
stop bit and any logic 1s at the end of a character count toward the full character time of
idle. When UART_C1[ILT] is set, the idle bit counter does not start until after a stop bit
time, so the idle detection is not affected by the data in the last character of the previous
message.
33.4.3.2.2 Address-mark wakeup
When wake is set, the receiver is configured for address-mark wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a, or two, if
UART_BDH[SBNS] = 1, logic 1 in the most significant bits of a received character,
eighth bit when UART_C1[M] is cleared and ninth bit when UART_C1[M] is set.
Address-mark wakeup allows messages to contain idle characters, but requires the msb
be reserved for use in address frames. The one, or two, if UART_BDH[SBNS] = 1, logic
1s msb of an address frame clears the UART_C2[RWU] bit before the stop bits are
received and sets the UART_S1[RDRF] flag. In this case, the character with the msb set
is received even though the receiver was sleeping during most of this character time.
33.4.4 Interrupts and status flags
The UART system has three separate interrupt vectors to reduce the amount of software
needed to isolate the cause of the interrupt.
Chapter 33 Universal asynchronous receiver/transmitter (UART1 and UART2)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 665