NXP Semiconductors MKW01Z128, Reference Manual

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and generates an interrupt if enabled. When UART_S2[RWUID] is one, any idle
condition sets the UART_S1[IDLE] flag and generates an interrupt if enabled, regardless
of whether UART_C2[RWU] is zero or one.
The idle-line type (UART_C1[ILT]) control bit selects one of two ways to detect an idle
line. When UART_C1[ILT] is cleared, the idle bit counter starts after the start bit so the
stop bit and any logic 1s at the end of a character count toward the full character time of
idle. When UART_C1[ILT] is set, the idle bit counter does not start until after the stop bit
time, so the idle detection is not affected by the data in the last character of the previous
message.
32.3.3.2.2 Address-mark wakeup
When wake is set, the receiver is configured for address-mark wakeup. In this mode,
UART_C2[RWU] is cleared automatically when the receiver detects a logic 1 in the most
significant bit of a received character.
Address-mark wakeup allows messages to contain idle characters, but requires the msb
be reserved for use in address frames. The logic 1 in the msb of an address frame clears
the UART_C2[RWU] bit before the stop bits are received and sets the UART_S1[RDRF]
flag. In this case, the character with the msb set is received even though the receiver was
sleeping during most of this character time.
32.3.3.2.3 Match address operation
Match address operation is enabled when the UART_C4[MAEN1] or
UART_C4[MAEN2] bit is set. In this function, a frame received by the UART_RX pin
with a logic 1 in the bit position immediately preceding the stop bit is considered an
address and is compared with the associated MA1 or MA2 register. The frame is only
transferred to the receive buffer, and UART_S1[RDRF] is set, if the comparison matches.
All subsequent frames received with a logic 0 in the bit position immediately preceding
the stop bit are considered to be data associated with the address and are transferred to the
receive data buffer. If no marked address match occurs then no transfer is made to the
receive data buffer, and all following frames with logic zero in the bit position
immediately preceding the stop bit are also discarded. If both the UART_C4[MAEN1]
and UART_C4[MAEN2] bits are negated, the receiver operates normally and all data
received is transferred to the receive data buffer.
Match Address operation functions in the same way for both MA1 and MA2 registers.
Chapter 32 Universal asynchronous receiver/transmitter (UART0)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 641