NXP Semiconductors MKW01Z128, Reference Manual

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SPIx_C1 field descriptions (continued)
Field Description
When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode,
SS pin function is slave select input.
1 When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave
mode, SS pin function is slave select input.
When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS
pin function is slave select input.
0
LSBFE
LSB First (shifter direction)
This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data
register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with the most significant bit.
1 SPI serial data transfers start with the least significant bit.
31.3.5 SPI Match Register low (SPIx_ML)
This register, together with the MH register, contains the hardware compare value. When
the value received in the SPI receive data buffer equals this hardware compare value, the
SPI Match Flag in the S register (S[SPMF]) sets.
In 8-bit mode, only the ML register is available. Reads of the MH register return all
zeros. Writes to the MH register are ignored.
In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the MH or ML register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent value into the SPI match registers.
Address: Base a 4h offset
Bit 7 6 5 4 3 2 1 0
Read
Bits[7:0]
Write
Reset 0 0 0 0 0 0 0 0
SPIx_ML field descriptions
Field Description
Bits[7:0] Hardware compare value (low byte)
Chapter 31 Serial Peripheral Interface (SPI)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 591