NXP Semiconductors MKW01Z128, Reference Manual

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PIT_TCTRLn field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
CHN
Chain Mode
When activated, Timer n-1 needs to expire before timer n can decrement by 1.
Timer 0 cannot be chained.
0 Timer is not chained.
1 Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to
Timer 1.
1
TIE
Timer Interrupt Enable
When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt will immediately cause an
interrupt event. To avoid this, the associated TFLGn[TIF] must be cleared first.
0 Interrupt requests from Timer n are disabled.
1 Interrupt will be requested whenever TIF is set.
0
TEN
Timer Enable
Enables or disables the timer.
0 Timer n is disabled.
1 Timer n is enabled.
28.3.7 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Access: User read/write
Address: 4003_7000h base + 10Ch (16d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 TIF
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIT_TFLGn field descriptions
Field Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 28 Periodic Interrupt Timer (PIT)
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 547