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Sub 1 GHz Transceiver Architecture Description
MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc.
5-7
5.6.2
FSK Modulation
FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the
feedback loop of the PLL. The large resolution of the sigma-delta modulator, allows for very narrow
frequency deviation. The frequency deviation F
DEV
is given by:
To ensure a proper modulation, the following limit applies:
NOTE
No constraint applies to the modulation index of the transmitter, but the
frequency deviation F
DEV
must exceed 600 Hz.
5.6.3
OOK Modulation
OOK modulation is applied by switching on and off the Power Amplifier. Digital control and smoothing
are available to improve the transient power response of the OOK transmitter.
5.6.4
Modulation Shaping
Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband
response of the transmitter. Both shaping features are controlled with
PaRamp
bits in
RegPaRamp
.
•
In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at
the input of the sigma-delta modulator. If the Gaussian filter is enabled when the MKW01Z128 is
in Continuous mode, DCLK signal on pin 10 (DIO1/DCLK) will trigger an interrupt on the MCU
each time a new bit has to be transmitted.
•
When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the
PA is turned on and off, to reduce spectral splatter.
NOTE
The transmitter must be restarted if the ModulationShaping setting is
changed, in order to recalibrate the built-in filter.
5.6.5
Power Amplifiers
Three power amplifier blocks are embedded in the transmitter. The first one (PA0) can generate up to +13
dBm into a 50 Ohm load. PA0 shares a common front-end pin RFIO with the receiver LNA.
PA1 and PA2 are both connected to pin PA_BOOST, allowing for two distinct power ranges:
•
Low power mode - where power out is -18 dBm < Pout < 13 dBm, with PA1 enabled
•
Higher power mode - when PA1 and PA2 are combined, providing up to +17 dBm to a matched
load.
F
DEV
F
STEP
Fdev 13 0
(
, )
=
F
DEV
BR
2
--------
500kHz
+
Summary of Contents for MKW01Z128
Page 7: ...MKW01xxRM Reference Manual Rev 3 04 2016 viii Freescale Semiconductor Inc...
Page 11: ...MKW01xxRM Reference Manual Rev 3 04 2016 xii Freescale Semiconductor Inc...
Page 133: ...MKW01Z128 MCU Reference Manual Rev 3 04 2016 2 Freescale Semiconductor Inc...
Page 233: ...Module clocks MKW01Z128 MCU Reference Manual Rev 3 04 2016 102 Freescale Semiconductor Inc...
Page 513: ...Interrupts MKW01Z128 MCU Reference Manual Rev 3 04 2016 382 Freescale Semiconductor Inc...
Page 633: ...CMP Trigger Mode MKW01Z128 MCU Reference Manual Rev 3 04 2016 502 Freescale Semiconductor Inc...