NXP Semiconductors MKW01Z128, Reference Manual

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MKW01xxRM Reference Manual, Rev. 3, 04/2016
Freescale Semiconductor, Inc. 5-1
Chapter 5
Sub 1 GHz Transceiver Architecture Description
This chapter describes the architecture and operation of the MKW01Z128 low-power, highly integrated
transceiver chip.
5.1 Overview
The MKW01Z128 transceiver is a single-chip integrated circuit ideally suited for today's high
performance ISM band RF applications. The transceivers's advanced features set, including state of the art
packet engine greatly simplifies system design while the high level of integration reduces the external
BOM to a handful of passive decoupling and matching components. It is intended for use as
high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex
bidirectional RF links, and where stable and constant RF performance is required over the full operating
voltage range of the device.
The transceiver is intended for applications over a wide frequency range, including the 433 MHz and
868 MHz European and the 902-928 MHz North American ISM bands. Coupled with a link budget in
excess of 135 dB, the advanced system features include a 66-byte TX/RX FIFO, configurable automatic
packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system
flexibility whilst at the same time significantly reducing MCU requirements.
The transceiver complies with both ETSI and FCC regulatory requirements
5.2 Simplified Block Diagram
Figure 5-1 shows a simplified block diagram of the MKW01Z128 transceiver.