NXP Semiconductors MKW01Z128, Reference Manual, Page: 493 / 884

If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and
the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS]
bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output
frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the
multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89
MHz at high-range.
In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal
reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication
factor could potentially push the microcontroller system clock out of specification and
damage the part.
20.5.3 MCG mode switching
When switching between operational modes of the MCG, certain configuration bits must
be changed in order to properly move from one mode to another.
Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS],
or C2[EREFS0], the corresponding bits in the MCG status register (PLLST, IREFST,
CLKST, IRCST, or OSCINIT) must be checked before moving on in the application
software.
Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV]
and C5[PRDIV0]) is set properly for the mode being switched to. For instance, in PEE
mode, if using a 4 MHz crystal, C5[PRDIV0] must be set to 5'b000 (divide-by-1) or
5'b001 (divide-by-2) to divide the external reference down to the required frequency
between 2 and 4 MHz
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL
multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits.
Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1.
The table below shows MCGOUTCLK frequency calculations using C1[FRDIV],
C5[PRDIV0], and C6[VDIV0] settings for each clock mode.
Table 20-4. MCGOUTCLK Frequency Calculation Options
Clock Mode f
MCGOUTCLK
1
Note
FEI (FLL engaged internal) f
int
× F Typical f
MCGOUTCLK
= 21 MHz
immediately after reset.
FEE (FLL engaged external) (f
ext
/ FLL_R) × F f
ext
/ FLL_R must be in the range of
31.25 kHz to 39.0625 kHz
FBE (FLL bypassed external) OSCCLK OSCCLK / FLL_R must be in the
range of 31.25 kHz to 39.0625 kHz
Table continues on the next page...
Initialization / Application information
MKW01Z128 MCU Reference Manual, Rev. 3, 04/2016
362 Freescale Semiconductor, Inc.